Static random access memory

ABSTRACT

A method and apparatus for a four transistor SRAM comprising an array or block of cells. Each cell comprises a pair of pass transistors and a pair of pull-down transistors. In one embodiment of the invention, when the SRAM block is in a standby mode, the difference between the voltage at the gate and the voltage at the source of each pass transistor is greater than 0, and less than the threshold voltage of the pass transistor. In one embodiment of the invention a ground connection of the memory cell is switched such that when the SRAM block is in the standby mode, the ground connection is a virtual ground connection and when the SRAM block is in an active mode the ground connection is a global ground connection.

BACKGROUND

1. Field of the Invention

The present invention is related to the field of memory devices. Inparticular, the present invention is related to Static Random AccessMemory (SRAM).

2. Description of the Related Art

SRAM cells are commonly used to store information in electroniccircuits. As compared with Dynamic Random Access Memory (DRAM), SRAMhave faster access times and do not have to be refreshed. The evolutionof smaller SRAM cells, e.g., the four transistor (4T) SRAM cell caused asignificant improvement in the storage density on a given piece ofsilicon as compared with the six transistor (6T) SRAM cell.

FIG. 1 illustrates a conventional 4T SRAM. As illustrated in FIG. 1, aconventional 4T SRAM 100 typically comprises an array or a block of‘N+1’ rows and ‘M+1’ columns of SRAM cells. Each SRAM cell 105 comprisesa matched pair of P-channel Metal Oxide field effect Semiconductor(PMOS) transistors 102A-B (pass transistors) cross coupled with amatched pair of N-channel (NMOS) transistors 104A-B (pull-downtransistors). As illustrated in FIG. 1, a storage node 120 is formed bycoupling one end of the channel of PMOS transistor 102A, one end of thechannel of NMOS transistor 104A, and the gate of NMOS transistor 104B.So also, storage node 125 is formed by coupling one end of the channelof PMOS transistor 102B, one end of the channel of NMOS transistor 104B,and the gate of NMOS transistor 104A. The storage nodes 120 and 125store a binary bit and its complement respectively. Each PMOS transistor102A-B has the other end of its channel coupled to a precharge circuit135, the precharge circuit 135 is coupled to a power supply having avoltage of Vcc volts. As FIG. 1 illustrates, each of the memory cells iscoupled to a complementary pair of bitlines, indicated by BL0 and BL0#respectively, which are precharged by the precharge circuit 135 prior toa read or write operation (for a M+1 column SRAM, the M+1 column hasbitlines BLM and BLM# respectively).

The gate of each PMOS transistor 102A-B is coupled to a wordline that isdriven by a decoder circuit 130. The decoder circuit 130 is coupled to apower supply having a voltage of Vcc volts. The wordlines are indicatedby WL0-WLN (for a N+1 row SRAM) in FIG. 1, and are used to selectivelyenable memory cells to be read from or written to. The other terminal ofeach NMOS transistor 104A-B is coupled to a global ground connection110.

Reducing the size of the SRAM cell from six transistors to fourtransistors, in order to maximize SRAM cell density, causes the 4T SRAMcell to be less stable during read operations and to have a higher offstate leakage current as compared with the 6T SRAM cell. This is becausein the design of the 6T SRAM cell, the two additional transistorsprevent the bits on the storage nodes from changing their state. Inaddition, during read operations conventional 4T SRAM cells have aslower sensing speed and may leak causing the bits stored on the storagenodes of the SRAM cells to change their state (e.g., from a 0 to a 1 orvice versa). Moreover, in the off state, the 4T SRAM cells have a higherleakage current resulting in a higher power consumption.

BRIEF SUMMARY OF THE DRAWINGS

Example embodiments of the present invention are illustrated in theaccompanying drawings. The accompanying drawings, however, do not limitthe scope of the present invention. Similar references in the drawingsindicate similar elements.

FIG. 1 illustrates a conventional 4T SRAM.

FIG. 2 illustrates an SRAM according to one embodiment of the invention.

FIG. 3 illustrates a precharge circuit according to one embodiment ofthe invention.

FIG. 4 illustrates an SRAM with a switched ground connection accordingto one embodiment of the invention.

FIG. 5 illustrates a microprocessor using an SRAM according to oneembodiment of the invention.

FIG. 6 illustrates a computer system using an SRAM according to oneembodiment of the invention.

FIG. 7A illustrates a timing diagram for reading a bit stored in an SRAMcell according to one embodiment of the invention.

FIG. 7B illustrates a timing diagram for an SRAM block in a standbymode.

DETAILED DESCRIPTION

Described is a 4T static random access memory (SRAM). In one embodimentof the invention, an SRAM comprises an array or a block of cells. Eachcell in the block of cells comprises a matched pair of pass transistorscoupled with a matched pair of pull-down transistors. A storage node tostore a binary bit is formed by coupling one end of the channel of apass transistor, one end of the channel of a pull-down transistor, andthe gate of the other pull down transistor. The other end of the channel(i.e., the source terminal) of the pass transistors of each cell iscoupled to a precharge circuit having a power supply voltage of High Vccvolts. The gate of each pass transistor is coupled to a decoder circuithaving a power supply voltage of Low Vcc volts. In one embodiment of theinvention, when the SRAM block is in the standby mode i.e., when thecells in the SRAM block are not being read from or written to, thedifference between the voltages at the source and the gate of the passtransistors is greater than 0 and less than the threshold voltage of thepass transistors. In one embodiment of the invention, a groundconnection that couples each SRAM cell to a global ground connection, isswitched (e.g., by a transistor switch) such that, when the SRAM blockis in the standby mode, the ground connection is a virtual groundconnection, and when the SRAM block is in the active mode, i.e., whenthe SRAM block is enabled and one or more of the memory cells are beingread from or written to, the ground connection is substantially a globalground connection.

References in the specification to “one embodiment”, “an embodiment”,“an example embodiment”, etc., indicate that the embodiment describedmay include a particular feature, structure, or characteristic, butevery embodiment may not necessarily include the particular feature,structure, or characteristic. Moreover, such phrases are not necessarilyreferring to the same embodiment. Further, when a particular feature,structure, or characteristic is described in connection with anembodiment, it is submitted that it is within the knowledge of one ofordinary skill in the art to effect such feature, structure, orcharacteristic in connection with other embodiments whether or notexplicitly described. Parts of the description are presented usingterminology commonly employed by those of ordinary skill in the art toconvey the substance of their work to others of ordinary skill in theart.

In the following description and claims, the terms “coupled” and“connected”, along with derivatives such as “communicatively coupled”may be used. It should be understood that these terms are not intendedas synonyms for each other. Rather, in particular embodiments,“connected” may be used to indicate that two or more elements are indirect physical or electrical contact with each other. “Coupled” maymean that two or more elements are in direct physical or electricalcontact. However, “coupled” may also mean that two or more elements arenot in direct physical contact with each other, but still co-operate orinteract with each other.

FIG. 2 illustrates an SRAM according to one embodiment of the invention.As illustrated in FIG. 2, SRAM 200 comprises one or more SRAM cells 205arranged in N+1 rows and M+1 columns. Each SRAM cell 205 comprises amatched pair of P-channel Metal Oxide field effect Semiconductor (PMOS)transistors 202A-B (pass transistors) with a matched pair of N-channel(NMOS) transistors 204A-B (pull down transistors). As illustrated inFIG. 2, a storage node 220 is formed by coupling one end of the channelof PMOS transistor 202A, one end of the channel of NMOS transistor 204A,and the gate of NMOS transistor 204B. So also, a storage node 225 isformed by coupling one end of the channel of PMOS transistor 202B, oneend of the channel of NMOS transistor 204B, and the gate of NMOStransistor 204A. The storage nodes 220 and 225 are provided to store abinary bit and its complement respectively. Each PMOS transistor 202A-Bhas the other end of its channel coupled to a power supply, having aHigh Vcc voltage, through a precharge circuit 300.

FIG. 3 illustrates a precharge circuit according to one embodiment ofthe invention. As illustrated in FIG. 3, the precharge circuit 300comprises three PMOS transistors 310A-C. PMOS transistors 310A-B arecoupled to power supply 305 and to a complementary pair of bitlines BL0and BL0# (for SRAM cell 205) respectively. PMOS transistor 310C iscoupled between the complementary pair of bitlines BL0 and BL0#. Aprecharge control 325 from e.g., a memory controller (not shown) iscoupled to the gates of the PMOS transistors 310A-C. The prechargecircuit power supply 305 has a voltage of High Vcc volts. Therefore, theprecharge circuit 300 precharges the complementary pair of bitlines BL0and BL0# to a voltage of High Vcc volts prior to a read or writeoperation.

As illustrated in FIG. 2, the gates of each PMOS transistor 202A-B arecoupled to a wordline that is driven by a decoder circuit 230. Thewordlines, indicated by WL0-WLN (for a N+1 row SRAM), are used to turnthe PMOS transistors on and off. Decoder circuit 230 is coupled to asecond power supply (not shown) having a voltage of Low Vcc volts.Therefore, the decoder circuit 230 has a minimum output voltage ofsubstantially 0 volts and a maximum output voltage of Low Vcc volts,where Low Vcc volts is less than the High Vcc volts output of theprecharge circuit 300. In one embodiment of the invention, in additionto supplying the source voltage to precharge circuit 300, the powersupply 305, having a voltage of High Vcc volts, supplies the power to atleast sense amplifier 240. The sense amplifier 240, that is coupledbetween the complementary pair of bitlines BL0 and BL0#, senses avoltage differential across the complementary pair of bitlines BL0 andBL0# very rapidly and outputs the bit stored in the memory cell 205 tothe SRAM's data output line. The Low Vcc power supply supplying power tothe decoder circuit may supply power to other logic circuitry e.g.,control logic circuitry etc. Thus, two power supplies having differentpower supply voltages are used to supply power to circuits in an SRAMblock. When the SRAM block is in the standby mode, the differencebetween the voltages at the source and the gate of the pass transistorsis greater than 0 and less than the threshold voltage of the passtransistors. As FIG. 2 illustrates, the other terminal of each NMOStransistor 204A-B is coupled to a global ground connection 210.

FIG. 7A illustrates a timing diagram for reading a bit stored in an SRAMcell according to one embodiment of the invention. As FIG. 7Aillustrates, prior to a read operation, between times T0 and T1, thebitlines BL0 and BL0# are precharged to a High Vcc voltage by prechargecircuit 300. Thereafter at T1, a wordline e.g., WL0 is enabled bydecoder 230 asserting a voltage at the gate of PMOS transistors 202A-Bto cause the PMOS transistors to turn on. Assuming a ‘1’ is stored atstorage node 220 and a ‘0’ is stored at storage node 225, during theread operation (i.e., between times T1 and T2 of the active mode) PMOStransistor 202B and NMOS transistor 204B are enabled, and NMOStransistor 204A is disabled (due to the voltage present at theirrespective gates). During this time (i.e., between T1 and T2) prechargecontrol 325 is driven to High Vcc volts to turn off the PMOS transistors310A-C.

In order to maintain the bits stored at storage nodes 220 and 225 (whenthe SRAM block is in the active mode), the ratio of the ‘on’ resistanceof PMOS transistor 202B to the ‘on’ resistance of NMOS transistor 204Bis relatively large to prevent transistor 204A from being erroneouslyenabled and to cause the bits stored at storage nodes 220 and 225 tochange. If this were not true, then an impermissibly large ‘on’ statecurrent would flow through PMOS transistor 202B and through NMOStransistor 204B causing a higher voltage drop across NMOS transistor204B. The higher voltage drop across NMOS transistor 204B would causethe gate voltage of NMOS transistor 204A to increase. This increase involtage at the gate of NMOS transistor 204A causes transistor 204A toturn on thereby changing the state of the bit at storage node 220 from a‘1’ to a ‘0’. This change in state at storage node 220 causes NMOStransistor 204B to turn off changing the state of the bit at storagenode 225 from a ‘0’ to a ‘1’.

However, for the SRAM block in the standby mode the reverse is true, andit is desirable that the off resistance of the PMOS transistors aresmaller than the off resistance of the NMOS transistors in order tomaintain the integrity of the bits stored at storage nodes 220 and 225.In particular, it is desirable that the PMOS transistors 202A-B have alarger leakage current as compared with the NMOS transistors 204A-B inthe standby mode to prevent the bits stored on storage nodes 220 and 225from changing their state.

In order to balance these competing ohmic requirements between theactive and standby modes, the PMOS transistors 202A-B in the SRAM cell205 are made physically smaller as compared with the NMOS transistors204A-B during the manufacture of the SRAM. Smaller pass transistorsincrease the resistance of the pass transistors making the SRAM cell 205stable during the active mode.

FIG. 7B illustrates a timing diagram for an SRAM block in a standbymode. In the standby mode, the precharge circuit 300 holds the bitlinesBL0 and BL0# at a voltage of high Vcc volts. This is because theprecharge control 325 is held at 0 volts causing transistors 310A-C tobe turned on. Decoder circuit 230 disables the pass transistors 202A-Bby asserting a Low Vcc volts on the gates of the pass transistors viawordline WL0. In the standby mode, the difference between the voltageasserted by the decoder circuit 230 and the voltage asserted by theprecharge circuit 300, on the PMOS transistors 202A-B, is greater than 0and less than the threshold voltage of the PMOS transistors 202A-B. Thethreshold voltage of a PMOS transistor may be defined as the minimumvoltage between the source and the gate of the PMOS transistor requiredto turn the PMOS transistor is on. When the memory block is in thestandby mode, the PMOS transistors 202A-B are in the sub-thresholdregion of the PMOS operational characteristic curve. Since thesub-threshold leakage current increases significantly with the increaseof source to gate voltage of the PMOS transistors 202A-B, the PMOStransistors 202A-B have a larger leakage current in the standby mode.The larger leakage current of the PMOS transistors 202A-B enables thestorage nodes 220 and 225 to maintain the binary bits stored thereon.

FIG. 4 illustrates an SRAM with a switched ground connection accordingto one embodiment of the invention. FIG. 4 illustrates the SRAM of FIG.2 with one of the terminals of each NMOS transistor 204A-B coupled to aglobal ground connection 410 via NMOS transistor switch 450. AlthoughFIG. 4 illustrates an NMOS transistor switch, other embodiments of theinvention may use any switch (e.g., a bipolar transistor switch, anop-amp switch, etc.) to switch the ground connection between globalground 410 and a virtual ground 445. The NMOS transistor switch 450 iscontrolled by a sleep signal (SLP) from, e.g., a memory controller (notshown) that turns the NMOS transistor switch 450 on when the memoryblock is in the active mode, and off when the memory block is in thestandby mode. Thus, as illustrated in FIGS. 7A and 7B the NMOStransistor switch 450 is turned on by asserting a High Vcc volts on thegate of the NMOS transistor switch 450, and is turned off by asserting 0volts on the gate of the NMOS transistor switch 450. In the embodimentof FIG. 4, when the SRAM block is in the active mode, a High Vcc voltsis applied to the gate of the NMOS transistor switch 450 to minimize thevoltage drop across the drain and source of the NMOS transistor switch.In particular, the High Vcc volts is applied to the gate of the NMOStransistor switch to ensure that when the NMOS transistor switch 450 ison, the voltage drop across the NMOS transistor switch 450 issubstantially 0V, and the ground connection is substantially a globalground connection. Turning the NMOS transistor switch 450 off raises theground connection of the SRAM block from global ground 410 to a virtualground 445 reducing the leakage power consumed by the SRAM memory blockin the standby mode, while maintaining the desirable large leakagecurrents of the PMOS transistors 202A-B. In the standby mode, the higherthe virtual ground voltage the smaller is the leakage current. However,if the virtual ground voltage is raised too high, the data stored in thememory cell may become corrupt. Therefore, in one embodiment of theinvention the voltage level of the virtual ground connection 445 is lessthan the threshold voltage of the NMOS pull-down transistors 204A-B.Having the voltage level of the virtual ground connection 445 less thanthe threshold voltage of the NMOS pull-down transistors 204A-B,maintains the integrity of the data stored on storage nodes 220 and 225.Adjustments to control the precise voltage level of the virtual ground445 when the NMOS transistor switch 450 is off may be made bycontrolling the channel size of the NMOS transistor switch 450 duringmanufacture.

FIG. 5 illustrates a microprocessor using an SRAM according to oneembodiment of the invention. As illustrated in FIG. 5 microprocessor 500comprises an instruction pipeline subdivided into four processing units,i.e., the fetch/decode unit 535, the dispatch/execute unit 540, theretire unit 545, and the instruction pool 550. Instructions and data aresupplied to the four processing units through the bus interface unit525. The bus interface unit 525 obtains instructions and data fromexternal memory (not shown) via system bus 505 or from L2 cache/SRAM 520via bus 510, and stores the instructions and data in L1 cache/SRAM 530.In one embodiment of the invention, one or more of the L2 cache/SRAM 520and/or the L1 cache/SRAM 530 comprises SRAM cells as described abovewith respect to FIGS. 2 and 4. The fetch/decode unit 535 reads a streamof instructions from L1 cache/SRAM 560 and decodes them into a series of“micro-ops” that is sent to the instruction pool 550. The instructionpool 550 is basically a buffer that stores the micro-ops for thedispatch execute unit 540. The dispatch/execute unit 540 is anout-of-order unit that schedules and executes the micro-ops stored inthe instruction pool according to data dependencies and resourceavailability and temporarily stores the results of these speculativeexecutions. The retire unit 545 commits the results of the speculativelyexecuted micro-ops to permanent machine state and removes the micro-opsfrom the instruction pool. The retire unit 545 checks the status ofmicro-ops in the instruction pool looking for micro-ops that have beenexecuted and no longer have any dependencies with other micro-ops in theinstruction pool. It then retires completed micro-ops in their originalprogram order, taking into account interrupts, exceptions, breakpoints,and branch mispredictions. Although the embodiment of FIG. 5 uses anout-of-order processor to process instructions, other embodiments of theinvention may use a sequential processor or any other processor, such asa digital signal processor, so long as the SRAM used in the processor isas described with respect to FIGS. 2 and 4.

FIG. 6 illustrates a computer system using an SRAM according to oneembodiment of the invention. As illustrated in FIG. 6, the computersystem 600 may comprise one or more processors 610, and a chipset 620.Processors 610 may comprise SRAM 602 as illustrated with respect toFIGS. 2 and 4, and are coupled to chipset 620 via a processor bus 664.In one embodiment of the invention, the processor bus 664 is a frontside bus (FSB) as used with Intel® corporation's Pentium 4 processor.Chipset 620 may comprise one or more integrated circuit packages orchips.

In one embodiment of the invention chipset 620 includes processor businterface (I/F) logic 604 coupled between processor bus 664 and one ormore interfaces within chipset 620. In one embodiment of the invention,chipset 620 includes memory bus interface logic 606 to couple thechipset 620 to a memory/SRAM 630 via a memory bus 666. Memory/SRAM 630may include the SRAM as illustrated with respect to FIGS. 2 and 4. Inone embodiment of the invention, chipset 620 includes Input/Output (I/O)bus interface logic 612 coupled to I/O devices 613 via, e.g., I/O bus668. A second I/O bus interface logic 607 couples chipset 520 to anetwork controller 640 using, e.g., I/O bus 669.

In one embodiment of the invention, network controller 640 couples thecomputer system 600 to one or more remote computing devices 619. Forexample, network controller 640 may comprise an Ethernet controller, acable modem, a digital subscriber line (DSL) modem, etc. that may beused to couple the computer system 600 to one or more remote computingdevices 619.

A third I/O bus interface logic 608 couples chipset 620 to one or morestorage devices 614 using, e.g., a I/O bus 671. The storage devices 614may store program code and/or data permanently, e.g., on a hard disk, ora magnetic storage device. A graphics bus interface logic 609 coupleschipset 620 to a graphics controller 615 via a graphics bus 674. I/O busI/F logic 605 couples chipset 620 to super I/O controller 618 that iscoupled to, e.g., a keyboard/mouse 611 etc.

Graphics controller 615 is coupled to display device 616. In oneembodiment of the invention graphics controller 615 may include one ormore digital to analog converters (DACs) (not shown) and SRAM (notshown) as illustrated with respect to FIGS. 2 and 4 above. The SRAMstores color palette entries that are needed to generate the analogsignals to drive display device 616. A logical color number may be fedinto the address inputs (wordlines) of the SRAM to select a colorpalette entry. This color palette entry may be composed of threeseparate values corresponding to the three components (red, green, andblue) of the desired physical color. Each component value may be fed toa separate DAC, and the analog output from each of the DACs may becoupled to the electron gun (or equivalent for devices not using anelectron gun) of display device 616.

Thus a method and apparatus have been disclosed for a 4T SRAM. Whilethere has been illustrated and described what are presently consideredto be example embodiments of the present invention, it will beunderstood by those skilled in the art that various other modificationsmay be made, and equivalents may be substituted, without departing fromthe true scope of the invention. Additionally, many modifications may bemade to adapt a particular situation to the teachings of the presentinvention without departing from the central inventive concept describedherein. Therefore, it is intended that the present invention not belimited to the particular embodiments disclosed, but that the inventioninclude all embodiments falling within the scope of the appended claims.

1. A memory cell comprising: a pass transistor, a pull-down transistor,a first power supply, a second power supply, a precharge circuit, and adecoder circuit, each transistor having a threshold voltage, a gate anda channel, the channel having a first end and a second end, the secondend of the channel of the pass transistor coupled to the first end ofthe channel of the pull-down transistor, and the second end of thechannel of the pull-down transistor coupled to a ground connection, thefirst end of the channel of the pass transistor coupled to the firstpower supply via the precharge circuit and the gate of the passtransistor coupled to the second power supply via the decoder circuit,the first power supply and the second power supply each having adifferent power supply voltage. 2-31. (canceled)